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42063a?led?02/2013 features ? dual-string led driver for 2-color or 2 unequal v f leds ? phase shifted register controlled dimming (MSL2023) ? individual pwm inputs (msl2024) ? adaptively controls headroom of ac/dc or dc/dc, isolated or non-isolated topologies ? main led string driven by linear current controller ? drives external n-channel mosfet ? 3% current accuracy , no ripple current ? 8-bit dac for peak current control ? color-adjust led string uses floating buck controller ? drives external n-channel mosfet ? over 100:1 dimming range ? open and short led detection ? 8-bit dac allows changing current sense threshold ? i 2 c accessible driver settings and eeprom ? open-drain fault indicator output ? -40c to +105c operating temperature range typical applications ? general and architectural lamps ? high cri led fixtures ? down lights and recessed lights ? par lamps atmel led drivers MSL2023 / msl2024 2-string led driver with individual pwm dimming and adaptive headroom control for high cri led luminaires http://www..net/ datasheet pdf - http://www..net/
2 MSL2023/2024 [datasheet] 42063a?led?02/2013 1. introduction the MSL2023/24 led drivers for two-color systems include a linear current controller for the main string, typically for white leds, and a second floating buck controller for a color- adjust led string. both the switching and linear controllers drive external mosfets to provide flexibility over a wide range of power levels (led currents and voltages). the MSL2023/24 adaptively manage the voltage powering the main led string. a proprietary and patent pending efficiency optimizer algorithm controls the voltage output of any ac/dc or dc/dc isolated or non-isolated topology, including ultra-low bandwidth single-stage pfc flyback controller. the MSL2023/24 feature peak current control and individual string pwm dimming. the MSL2023 features individual, register controlled, 180 out of phase pwm dimming at 400hz. the msl2024 offers individual string pwm inputs. the MSL2023/24 operate from a 9.5v to 15v power supply. the main led string is driven by a high accuracy, ripple free linear current controller. the color-adjust string voltage regulat ion loop uses a constant off-time control algorithm to achieve stable control with good transient behavior. for flexibility of design, off-time is set using an external resistor. led current in both strings can be adjusted using internal 8-bit dacs. the MSL2023/24 are available in space-saving 24-pin 4x 4mm qfn package and operate over the extended -40c to 105c operating range. 2. ordering information note: 1. lead-free, halogen-free, rohs compliant package 3. application circuit ordering code description package (1) MSL2023in two string led driver 4 x 4mm 24-pin qfn msl2024in two string led driver 4 x 4mm 24-pin qfn single stage pfc flyback controller fbo a c mains white led string color led string bridge rectifier & emi filter d g s drv cs msl2024 led driver linear led driver mcu floating buck led driver pwm1 pwm2 vdd v in http://www..net/ datasheet pdf - http://www..net/
3 MSL2023/2024 [datasheet] 42063a?led?02/2013 4. absolute maximum ratings voltage with respect to agnd avin, pvin, en -0.3v to +16.5v vcc, pwm1, pwm2, fltb, sda, scl, toff, rext, fbo -0.3v to +5.5v vdd -0.3v to +2.75v cs, s -0.3v to vdd+0.3v d -0.3v to +22v g, d rv -0.3v to vin+0.3v pgnd -0.3v to +0.3v current (into pin) avin, pvin, drv, g (average) 100ma pvin (peak, =1% duty) 1a drv, g (peak, =1% duty) 1a pgnd (peak, =1% duty) -1a agnd, pgnd (average) -100ma all other pins 10ma continuous power dissipation at 70c 24-pin 4mm x 4mm vqfn (derate 21.8mw/c above ta = +70c) 1200mw ambient operating temperature range -40c to +105c junction temperature +125c storage temperature range -65c to +125c lead soldering temperature, 10s +300c http://www..net/ datasheet pdf - http://www..net/
4 MSL2023/2024 [datasheet] 42063a?led?02/2013 5. electrical characteristics avin = pvin = 12v, -40c t a 105c, typical operating circuit, unless otherwise noted. typical values at t a = +25c. parameter symbol conditions min. typ. max. unit dc electrical characteristics avin, pvin operating supply voltage 9.5 12 15 v avin operating supply current leds on at pwm = 100%, serial interface idle 10 ma avin idle supply current en = sleep = 1, all digital inputs = 0 7 10 ma pvin idle supply current en = sleep = 1, all digital inputs = 0 0 a avin disable supply current v en = 0, all digital inputs = 0 5 a vcc regulation voltage i vcc = 10mapeak (7) 4.5 5 5.5 v vdd regulation voltage i vdd = 10mapeak (7) 2.25 2.5 2.75 v pwm1, pwm2, scl, sda input high voltage 0.7 ? v vdd v pwm1, pwm2, scl, sda input low voltage 0.3 ? v vdd v en input high voltage 2 v en input low voltage 0.5 v en input hysteresis 100 mv sda, fltb output low voltage sinking 6ma 0.3 v scl, sda, pwm1, pwm2, fltb leakage current -5 5 ? a s current sense regulation voltage mref = 0x64 194 200 206 mv s current sense regulation voltage accuracy main string at 100% duty cycle, t a = 25 ? c, mref = 0x64 -3 +3 % s current sense regulation voltage temperature coefficient -220 ppm/oc g maximum output voltage avin - 3.5 avin - 2.0 v d regulation threshold eoctrl = 0xe5 0.9 1 1.1 v cs current sense regulation voltage caref = 0x64 200 mv drv impedance v drv = 12v, i drv = 20ma 5.6 9 ? v drv = 0v, i drv = -20ma 5.6 9 ? http://www..net/ datasheet pdf - http://www..net/
5 MSL2023/2024 [datasheet] 42063a?led?02/2013 notes: 1. minimum scl clock frequency is limited by the bus timeout feature, which resets the serial bus interface when either sd a or scl is held low for t timeout . 2. sda data valid acknowledge time is scl low to sda (out) low acknowledge time. 3. sda data valid time is minimum sda output data-valid time following scl low transition. 4. a master device must internally provide an sda hold time of at least 300ns to ensure an scl low state. 5. the maximum sda and scl rise times is 300ns. the maximum sda fall time is 250ns. this allows seri es protection resistors to b e connected between sda and scl inputs and the sda/scl bus lines without exceeding the maximum allowable rise time. 6. includes input filters on sda and sc l that suppress noise less than 50ns. 7. additional decoupling may be required when pulling current from vcc and/or vdd in noisy environments. 8. 2s minimum on time, 0% duty cycle is supported. pwm between 0% and 1% not guaranteed. fbo full scale current 170 255 340 ? a fbo lsb current 1.0 ? a thermal shutdown temperature temperature rising 133 c thermal shutdown hysteresis 15 c ac electrical characteristics drv t off timing r toff = 45.3k ? 0.5 ? s pwm input frequency pwm1 (8) 60 22,000 hz pwm2 (8) 100 500 hz pwm duty cycle pwm1, pwm2 1 100 % pwm duty cycle resolution MSL2023 0.024 % i2c switching characteristics scl clock frequency (1) 0.05 1,000 khz stop to start condition bus free time t buf 0.5 s repeated start condition hold time t hd:sta 0.26 s repeated start condition setup time t su:sta 0.26 s stop condition setup time t su:stop 0.26 s sda data hold time t hd:dat 5 ns sda data valid acknowledge time (2) 0.05 0.55 s sda data valid time (3) 0.05 0.55 s sda data set-up time t su:dat 100 ns scl clock low period t low 0.5 s scl clock high period t high 0.26 s sda, scl fall time t f (4) , (5) 120 ns sda, scl rise time t r 120 ns sda, scl input suppression filter period (6) 50 ns bus timeout t timeout (1) 25 ms parameter symbol conditions min. typ. max. unit http://www..net/ datasheet pdf - http://www..net/
6 MSL2023/2024 [datasheet] 42063a?led?02/2013 typical operating characteristics figure 5-1. start-up behavior, pwm = 10% duty cycle. figure 5-2. start-up behavior, pwm = 90% duty cycle. v led fbo i in i main v led fbo i in i main http://www..net/ datasheet pdf - http://www..net/
7 MSL2023/2024 [datasheet] 42063a?led?02/2013 figure 5-3. MSL2023 operation, pwm = 10% duty cycle. figure 5-4. MSL2023 operation, pwm = 90% duty cycle. i main i ca i main i ca http://www..net/ datasheet pdf - http://www..net/
8 MSL2023/2024 [datasheet] 42063a?led?02/2013 figure 5-5. msl2024 operation, pwm = 10% duty cycle. figure 5-6. msl2024 operation, pwm = 90% duty cycle. pwm1 in i main pwm2 in i ca pwm1 in i main pwm2 in i ca http://www..net/ datasheet pdf - http://www..net/
9 MSL2023/2024 [datasheet] 42063a?led?02/2013 figure 5-7. fault response, string open circuit. figure 5-8. fault response, led short circuit. pwm in fltb i main i ca pwm in fltb i main i ca http://www..net/ datasheet pdf - http://www..net/
10 MSL2023/2024 [datasheet] 42063a?led?02/2013 figure 5-9. input current vs. input voltage. figure 5-10. average led current vs. input pwm duty cycle. 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 6 7 8 9 10 10 11 12 13 14 15 i in (a) i in (ma) v in (v) f in = 400hz pwm = 50% i in i sleep i shdn 0 20 40 60 80 100 0 50 100 led current (%fs) duty cycle (%) f in = 400hz main string http://www..net/ datasheet pdf - http://www..net/
11 MSL2023/2024 [datasheet] 42063a?led?02/2013 figure 5-11. v cc and v dd regulation. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 20406080100 v out (v) i out (ma) f in = 400hz pwm = 50% vcc vdd http://www..net/ datasheet pdf - http://www..net/
12 MSL2023/2024 [datasheet] 42063a?led?02/2013 6. block diagram figure 6-1. MSL2023 block diagram. regulators avin rext 1.2v current generator g s dac efficiency optimizer fbo drv c off s r q qb vref cs control logic en fault detect fltb toff current generator oscillator d vcc vdd pvin mux dac start clock vref main duty cycle register 400hz pwm generator vref pgnd agnd MSL2023 color adjust duty cycle register serial interface scl sda http://www..net/ datasheet pdf - http://www..net/
13 MSL2023/2024 [datasheet] 42063a?led?02/2013 figure 6-2. msl2024 block diagram. regulators avin rext 1.2v current generator g s dac pwm1 efficiency optimizer fbo drv c off s r q qb vref cs control logic en fault detect fltb toff current generator oscillator d vcc vdd pvin mux dac start clock vref pwm2 vref pgnd agnd msl2024 serial interface scl sda http://www..net/ datasheet pdf - http://www..net/
14 MSL2023/2024 [datasheet] 42063a?led?02/2013 7. pinout and pin description 7.1 pinout ? MSL2023 and msl2024 7.2 pin descriptions name pin description MSL2023 msl2024 fbo 1 1 feedback output feedback output from efficiency optimizer. connect fbo to the led power supply regulation feedback node to control v led . when unused connect fbo to vcc. en 2 2 enable input (active high) drive en high to turn on the MSL2023/24, drive en low to turn it off. for automatic start-up connect en to avin. taking en high initiates a turn-on sequence. see ?turn-on sequence? on page 19 for details. cgnd 3, 8, 12 12 connect to ground . connect cgnd to agnd pwm1 ? 3 pwm1 dimming input drive pwm1 with a pulse-width modulated signal to control led brightness of the main string. see ?pwm and led brightness? on page 24 for details. scl 4 4 serial clock input scl is the i2c serial interface clock input. see ?i2c serial interface ? on page 30 for details. sda 5 5 serial data input/output sda is the i2c serial interface data i/o. see ?i2c serial interface ? on page 30 details. fltb 6 6 fault output (open drain, active low) fltb sinks current to agnd when a fault condition exists. toggle en low then high to clear fltb, or clear faults through the serial interface (see ?fault status register (faultstat, 0x23), read only? on page 28 ). use the serial interface to access fault information and to enable/disable fault response. 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 10 11 12 24 23 22 21 20 19 fbo en cgnd scl sda fltb s nc pvin drv pgnd cs vdd agnd vcc avin d g nc cgnd rext toff dnc cgnd MSL2023 (top view) 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 10 11 12 24 23 22 21 20 19 fbo en pwm1 scl sda fltb s nc pvin drv pgnd cs vdd agnd vcc avin d g nc pwm2 rext toff dnc cgnd msl2024 (top view) http://www..net/ datasheet pdf - http://www..net/
15 MSL2023/2024 [datasheet] 42063a?led?02/2013 nc 7, 17 7, 17 no internal connection pwm2 ? 8 pwm2 dimming input drive pwm2 with a pulse-width modulated signal to control led brightness of the color-adjust string. see ?pwm and led brightness? on page 24 for details. rext 9 9 external resistor connect a 46.4k ? , 1% resistor from rext to agnd. toff 10 10 off-time set input a resistor from toff to agnd cont rols the constant off time for t he color-adjust string floating buck converter, where r toff = t off * (90.9 x 10 9 ), with t off in seconds and r toff in ohms. for example, an off time of 0.5s results in a resistor value of 45.3k ? (to the nearest 1% value). dnc 11 11 do not connect do not make external connection to dnc. cs 13 13 current sense input for the color-adjust string connect cs to the external current sense resistor of the color-adjus t string. the default current sense threshold is 200mv. pgnd 14 14 power ground pgnd is the ground connection for the fet ga te drivers. connect pgnd to agnd close to the MSL2023/2024. drv 15 15 gate drive for color-adjust (floating buck regulator) mosfet connect drv to the gate of the external power mosfet. pvin 16 16 power voltage input (12v nominal) pvin powers drv, the floating buck fet gate driv er. bypass pvin to pgnd with a 1.0f or greater capacitor. s 18 18 source sense input for main led string mosfet connect s to the source of the external mosfet, and to the current sense resistor for the main led string. the current sense threshold is 200mv. g 19 19 gate output for main string mosfet connect g to the gate of the main string external mosfet. d 20 20 drain output for main string mosfet connect d to the drain of the main string external mosfet. avin 21 21 analog voltage input (12v nominal) avin is the power input to the MSL2023/2024. bypass avin to agnd with a 1.0f or greater capacitor placed close to avin. vcc 22 22 5v internal voltage connect 10uf bypass capacitor from vcc to agnd. name pin description MSL2023 msl2024 http://www..net/ datasheet pdf - http://www..net/
16 MSL2023/2024 [datasheet] 42063a?led?02/2013 8. typical application circuit MSL2023/24 controlling the output of an isolated pfc controller; a linear current sink regulates the white led current and a floating buck converter regulates the color led string current. figure 8-1. MSL2023 typical application circuit. agnd 23 23 analog ground connect agnd to system ground. vdd 24 24 2.5v internal voltage connect 10f bypass capacitor from vdd to agnd. ep ep ep exposed pad connect ep to a large copper pl ane connected to pgnd and agnd. name pin description MSL2023 msl2024 g drv avin 12v agnd ac-dc isolated with pfc sda scl MSL2023 led driver rext cs + - 1.5 2.7 fltb fbo en white leds color leds pgnd vac 330h d pvin vcc vdd toff s 46.4k 10f 10f 1f 1f 45.3k irfr110 fdd3860 mbr0560 r d 100k c http://www..net/ datasheet pdf - http://www..net/
17 MSL2023/2024 [datasheet] 42063a?led?02/2013 figure 8-2. msl2024 typical application circuit. g drv avin 12v agnd ac-dc isolated with pfc sda msl2024 led driver rext cs + - 1.5 2.7 fltb fbo en white leds color leds pgnd vac 330h d pvin vcc vdd toff s 46.4k 10f 10f 1f 1f 45.3k irfr110 fdd3860 mbr0560 r d 100k pwm1 pwm2 scl c http://www..net/ datasheet pdf - http://www..net/
18 MSL2023/2024 [datasheet] 42063a?led?02/2013 9. detailed description table 9-1. device selection guide, led brightness control by part number. note: 1. access registers through i 2 c serial interface. the MSL2023/24 drive two led strings, the main string and the co lor-adjust string. the main string leds are typically white and used to provide an accurate light intensity control. the color-adjust string leds are used to control the color temperature. the combined light output is a blend, with intent to offer a warmer high cri light for example, than what white leds can alone produce. the main string is directly controlled by a pulse width modulated (pwm) constant current controller (current sink to ground). an efficiency optimizer (eo) output controls the main string voltage, via feed- back to the led string power supply, to minimize the voltage across the led current controller, minimizing power loss. the color-adjust string is regulated by a floating buck controller. the buck controller converts the voltage of the main string?s supply to a voltage appropriate for the color-adj ust leds. additionally, the MSL2023/24 have programmable 8-bit registers that allows adjustment of the current by changing the source feedback reference voltages (see ?block diagram? on page 12 ). 10. fault conditions the MSL2023/24 detect fault conditions, and take corrective action when faults are verified. string open circuit and led short circuit conditions of the co lor-adjust string are monitored. when one of these faults occurs, fltb pulls low to indicate a fault condition and the colo r-adjust leds turn off. read fault status register 0x23 to determine the fault type and to clear the faults, or clear faul ts by toggling en low then high. faults that persist re- establish the fault response. mask string faults using fault di sable register 0x22. clear string faults by toggling en low then high, or with ?fault disable register (fault, 0x22)? on page 27 . for the main led string when an led open occurs the v led voltage will reach the maximum allowed. over temperature protection puts the device to sleep when the die temperature is above 147 ? c. the device turns back on when the die temperature falls below 127 ? c, and normal operation resumes. while asleep, the i 2 c interface remains active (see ?fault disable register (fault, 0x22)? and ?fault status register (faultstat, 0x23), read only? on page 28 for more information about thermal shutdown). part led brightness control pwm dimming frequency main string color adjust string MSL2023 main pwm register (1) color adjust pwm register (1) 400hz msl2024 duty cycle at the pwm1 input duty cycle at the pwm2 input input frequency main: 60hz to 22khz (minimum t on = 2s) ca: 100hz to 500hz http://www..net/ datasheet pdf - http://www..net/
19 MSL2023/2024 [datasheet] 42063a?led?02/2013 table 10-1. fault conditions, response and recovery. 11. applications information 11.1 turn-on sequence when power is applied the eeprom contents copy into the c ontrol registers, setting up the device for operation; any previously programmed control register settings are lost unless they are programmed into the eeprom ( page 25 ). the MSL2023/24 wait for 250ms to allow the ac/dc or dc/dc input stage to establish the default voltage. the MSL2023/24 then starts to optimize the led string voltage (v led ), and then begin to drive the led strings. it is critical that the ac/dc or dc/dc converter that powers the led strings reaches it s nominal output voltage in less than 250ms after power is applied. when the 250ms start-up delay is complete the effici ency optimizer adjusts the led voltage to the proper level to drive the main string. after the voltage is set, normal pwm operation begins for both the main and color-adjust strings. 11.2 setting the main st ring current with r s the main string led current regulates by monitoring the voltage at the s pin, the main string mosfet source resistor connection. the default feedback voltage at the s pin is 200mv. choose the string current sense resistor r s using: where i led is the main string regulation current. the main st ring reference voltage (mref) register 0x20 sets the feedback voltage to 200mv, at 2mv per lsb. the regulation voltage, v s(fb) , is: where mref is the decimal equivalent of the value in register 0x20. the default value for mref is 0x64, for a feedback voltage of 0.2v. change the feedback voltage by changing the value in register 0x20 using the serial interface. led average current is within 3% of targeted value when a 1% resistor is used for r s . 11.3 setting ac/dc output voltage the efficiency optimizer output, fbo, connects to the ac /dc or dc/dc converter?s output voltage feedback node, and pulls current from the node to force the converter?s output voltage up. the MSL2023/24 works with any input power converter topology that uses a resistor divider to set its output voltage. additionally, the two strings will operate off of independent rails. operation with and ac/dc pfc converter is described below. select the two resistors that set the nominal led power s upply?s output voltage by first determining the minimum output voltage using: fault response recovery action die temperature > 147c asleep (i 2 c still active) when die temperature falls below 127c operation resumes color-adjust string has shorted leds color-adjust string turns off, fltb pulls low, and bit 0 of the fault status register 0x23 sets high correct the short condition in led string. toggle en low to high to resume operation, or clear faults using register 0x22 ( page 27 ) color-adjust string is open circuit color-adjust string turns off, fltb pulls low, and bit 1of the fault status register 0x23 sets high correct the open condition in led string. toggle en low to high resume operation, or clear faults using register 0x22 ( page 27 ) r s 0.2 i led ----------- - ? = v sfb ?? 0.002 mref ? ?? v = http://www..net/ datasheet pdf - http://www..net/
20 MSL2023/2024 [datasheet] 42063a?led?02/2013 where v fmin is the minimum led forward voltage for the main string leds at the expected led current, n is the number of leds in the string, and 0.2v is the minimum overhead required for the current sense resistor and the fet. then determine the maximum output voltage using: where v fmax is the maximum led forward voltage for the main string leds at the operating led current, n is the number of leds in the string, and 1.2v is the maximum overhead required for the current sense resistor and the fet. determine the value for the upper voltage setting resistor using: where 170 ? a is the minimum fbo full scale current. determine the lower resistor using: where v fb is the feedback regulation voltage of the switch mode converter. 11.4 selecting the main string mosfet the main string mosfet sinks the string curr ent to ground through current sense resistor r s . output g drives the gate of the mosfet at up to vin - 2.0v. select a mosfet wi th a low rds(on) and a maximum drain-source voltage of at least 20% greater than: where 340a is the maximum fbo full scale current. 11.5 selecting the drain resistor ? r d the drain resistor, r d in the ?typical application circuit ? on page 16 , connects the MSL2023/24 to the drain of the main string external mosfet. use a 100k ? for r d . v out min ?? v fmin ?? n ?? 0.2 v + ? ? v out max ?? v fmax ?? n ?? 1.2 v + ? = r top v out max ?? v out min ? ?? ? 170 10 6 ? ? ---------------------------------------------------------------- - ? ? r bottom r top v fb v out min ?? v fb ? ------------------------------------------- - ? ? = v fb r top r bottom ------------------------ 1 + ?? ?? 340 ? ar top ? + http://www..net/ datasheet pdf - http://www..net/
21 MSL2023/2024 [datasheet] 42063a?led?02/2013 11.6 selecting the color-adjust string floating buck components figure 11-1. floating buck led driver. the MSL2023/24 includes a driver for a constant off-time floating buck topology, shown in figure 11-1 , to convert the main string voltage to a value appropriate for the color-adjus t led string. the buck is operated in continuous conduction mode. continuous conduction operation is assured when t he peak-to-peak ripple current in the inductor, ? i l , is less than twice the average led current. a peak-to-peak ripple current magnit ude of 15% of the average led on-current is suggested, i.e. a where i ave is the average color-adjust led string on-current. choose i ave appropriate for the color-adjust leds ( figure 11-1 on page 21 and figure 11-2 on page 22 ) and calculate the peak string on-current using a drv cs r cs color leds (color-adjust string) l o v led d 1 toff r toff c o c i q pgnd v buck + - white leds (main string) i ave MSL2023/24 led driver ? i l 0.15 i ave = i peak i ave ? i l 2 -------- + = http://www..net/ datasheet pdf - http://www..net/
22 MSL2023/2024 [datasheet] 42063a?led?02/2013 figure 11-2. color-adjust string led on-current details. the color-adjust string led on-current regulates by monito ring the voltage at cs, the color-adjust string fet source resistor connection. the reference voltage v csfb for cs is 200mv ( v csfb is 200mv by default, and is adjustable through the serial interface; see the register definitions for details about changing v csfb ). choose the current sense resistor r cs using determine v buck , the voltage across the color-adjust leds, using v where n is the number of leds in the string and v f is the forward voltage drop of the leds at i peak . the duty ratio of mosfet q is where v led is the main string voltage, figure 11-1 on page 21 . the constant off-time of the mosfet is t off and calculated in seconds using s where f s is the selected switching frequency in hz. use 100khz to 1mhz for f s . set t off with resistor r toff from toff to gnd ( figure 11-1 on page 21 ), whose value is choose the inductor value using h use a ferrite inductor with a saturation current at least 50% higher than the peak current flowing in it: a note here a particular advantage of constant off-time operation of the buck converter is that ripple current is independent of the input voltage. the circuit prov ides a constant average led current, i ave , but the buck converter actually regulates the peak inductor current, i peak ( figure 11-1 on page 21 and figure 11-2 on page 22 ). from the equation for the inductor value l 0 above, we see that because t off is constant, and v buck is relatively constant, the ripple current ? i l is also constant, so that i ave is a constant, as desired. if the main string voltage changes, the switching frequency changes to keep the on-time constant, thus the ripple current is independent of the input voltage. i peak i ave inductor current led current (when using c o ) t off t i ?i l r cs v csfb i peak ---------------- ? = v buck nv f = d v buck v led ----------------- = t off 1 d ? f s ------------ - = r t off t off 90.9 10 9 ? ??? = l o v buck t off ? ? i l ----------------------------- - = i l sat 1.5 i peak ? ? http://www..net/ datasheet pdf - http://www..net/
23 MSL2023/2024 [datasheet] 42063a?led?02/2013 this topology does not require an output capacitor, c o in figure 11-1 on page 21 . when used, c o steers the inductor?s ripple current away from the leds but reduces the accuracy of pwm dimming because the voltage across it cannot change quickly. when using c o , a ceramic capacitor of between 1.0f and 10f is adequate, with a voltage rating higher than v buck . the output capacitor of the ac/dc converter that produces the main string voltage, c i in figure 11-1 on page 21 , doubles as the buck?s input capacitor. the capacitor?s function is to provide a smooth voltage to the buck converter. it should be able to handle the r.m.s. ripple current of the buck converter, which is approximately equal to a this ripple current peaks at a duty ratio of d = 0.5. select an n-channel mosfet for q with a maximum drain-source voltage at least 25% above v led . the r.m.s. current in the mosfet is approximately equal to a the mosfet conduction power loss due to this current is w where r ds is the hot on-resistance of the mosfet, which can be found in the mosfet datasheet, and is typically 1.5 to 1.8 times greater than the cold resistance. the mosfet wil l also incur switching losses, which can be difficult to calculate exactly. a good rule-of-thumb is to choose a mo sfet in a package that dissipates at least four times p con . the average current in the output rectifier d 1 is a and the power dissipated in the rectifier due to conduction is w where v on is the voltage drop across the rectifier at the forward current of i d1 . pick a rectifier with an average current rating at least 50% higher than i d1 . use a schottky rectifier if the led voltage is less than 50v. the schottky rectifier?s voltage rating should be at least 25% higher than v led . schottky rectifiers have very low on-state voltage and very fast switching speed, but at high voltage and high temperatures their leakage current becomes significant. the power dissipated in the schottky rectifier due to the leakage current at any temperature and duty ratio is w where i r is the reverse leakage current, found in the diode?s datasheet. this power must be added to the conduction power loss. w make sure that the rectifier?s total power dissipation is within the rectifier?s specifications. i c i i ave d 1 d ? ?? = i q i ave d = d r i r i p ds ave ds q con 2 2 ? ? i d i i ave 1 d ? ?? = p con d 1 i d 1 v on = p lkg v led i r d = p d 1 p con d p lkg + = http://www..net/ datasheet pdf - http://www..net/
24 MSL2023/2024 [datasheet] 42063a?led?02/2013 11.7 pwm and led brightness figure 6-1 on page 12 is a block diagram that shows how the MSL2023 controls the brightness of the leds. the duty cycle of each string equals the value programmed into the 12-bit pwm control registers mainduty[11:0] and coloradjustduty[11:0], (registers 0x34 through 0x37). t he frequency of the pwm dimming is 400hz. the dimming signals for the two strings are 180o out of phase. figure 6-2 on page 13 is a block diagram that shows how the msl2024 controls the brightness of the leds. the duty cycle of each string equals the duty cycle of the inputs at pwm1 (main string) and pwm2 (color-adjust string). the frequency of each string?s pwm dimming signal equals the fr equencies of the respective input signals. the frequency range of the pwm1 input is 120hz to 22khz, while the minimum on-time for the main string driver output g is 2s. the frequency range of the pwm2 input is 200hz to 500hz. 12. control registers table 12-1. register map (1) . notes: 1. do not change the contents of undefined bits or unlisted registers. address and register name function default value (2) bit functions d7 d6 d5 d4 d3 d2 d1 d0 control and monitor registers 0x00 to 0x1f ram 0xxx free ram 0x20 mref main string feedback reference voltage 0x64 m ref = 2mv per lsb 0x21 caref color-adjust string reference feedback voltage 0x64 ca ref = 2mv per lsb 0x22 fault disable color-adjust fault disable 0x00 ? ? ? ? ? tsdmask ocdis scdis 0x23 faultstat fault status read only ? ? ? ? ?tsdocfltscflt 0x24 sleep configuration 0x00 ? ? ? ? ? ? ? sleep 0x34 mdutyhigh main string duty cycle high byte 0xff mainduty[11:4] MSL2023 only 0x35 mdutylow main string duty cycle low bits 0x0f ? ? ? ? mainduty[3:0] MSL2023 only 0x36 cadutyhigh color adjust string duty cycle high byte 0xff coloradjustduty[11:4] MSL2023 only 0x37 cadutylow color adjust string duty cycle low bits 0x0f ? ? ? ? coloradjustduty[3:0] MSL2023 only 0x40 eoctrl efficiency optimizer 0xe5 ? ? ? ? dthresh[3:0] 0x60 e2addr eeprom address 0x00 ? eeprom address pointer 0x61 e2ctrl eeprom control 0x00 ? ? ? ? ? rwctrl[2:0] http://www..net/ datasheet pdf - http://www..net/
25 MSL2023/2024 [datasheet] 42063a?led?02/2013 2. unless changed through the eeprom, these default values l oad at power-up, and when en is taken from low to high. 12.1 eeprom and power-up defaults an on-chip eeprom holds all the default register values ( table 12-1 on page 24 ). at power-up the data in the eeprom automatically copy directly to control register s 0x00 thru 0x51, setting up the device for operation. any changes made to registers 0x00 thru 0x51 after power-up ar e not reflected in the eeprom and are lost when power is removed from the device, or when the enable input en is forced low. if a different power-up condition is desired program the values into the eeprom via the serial interface as explained in the next section, or contact the factory to inquire about ordering a customized power-up setting. 12.2 eeprom address and c ontrol/status registers the eeprom can be visualized as an image of the control r egisters from 0x00 thru 0x51. change an eeprom register value by writing the new value into the associated control register, and then instructing the device to program that value into the eeprom. two control registers facilitate this pr ocess, the eeprom address register e2addr (0x60), and the eeprom control register e2ctrl (0x61). into e2addr write the location of the data that is to be programmed into the eeprom, and write 0x03 to e2ctrl to command the device to program that data into the eeprom. programming the eeprom takes a finite amount of time; after sending a co mmand to e2ctrl wait 5ms, then end the write cycle by writing 0x00 to e2ctrl. example: change the string current feedback voltage mref to 100mv. commands: to register 0x20 (mref) write 0x 32 (the new value for mref). to register 0x60 (e2addr) write 0x20 (the address of the mref register). to register 0x61 (e2ctr l) write 0x03 (the command to copy the value to eeprom). wait 5ms. to register 0x61 (e2ctrl) write 0x00, to turn off eeprom access. result: the value 0x32, located in the mref register, is programmed into the eeprom and becomes the new power- up default value for mref. summary: ? 0x20 32 ? 0x60 20 ? 0x61 03 ? wait 5ms ? 0x61 00 e2ctrl provides additional functions beyond simply progra mming a register?s value into the eeprom. data may be transferred in either direction, from the registers to the eeprom, or from the eeprom to the registers. register data may be transferred into or out of the eeprom in groups of eight, a page at a time. the page address boundaries are predefined, and e2addr must be loaded with the address of the first byte of the page that is to be copied. page addresses begin at 0x00 and increment by eight, with the second page beginning at 0x08, the third at 0x10, etc. to program a full page of data into the eeprom, write the address of the page?s first byte to e2addr, and write 0x04 to e2ctrl. wait 5ms, and then end the write cycle by writing 0x00 to e2ctrl. when finished accessing the eeprom always write 0x00 to e2ctrl to bloc k inadvertent eeprom read/writes. table 12-3 on page 26 details the functions available through e2ctrl. http://www..net/ datasheet pdf - http://www..net/
26 MSL2023/2024 [datasheet] 42063a?led?02/2013 table 12-2. eeprom address register (e2addr, 0x60), defaults highlighted . table 12-3. eeprom cont rol register (e2ctr l, 0x61), defaults highlighted . 13. detailed register descriptions the MSL2023/24 registers are summarized in ?control registers? on page 24 . detailed register information follows. 13.1 ram (0x00 through 0x1f) 32 bytes of ram accessible through the i 2 c serial interface. copy data from ram into eeprom (see ?eeprom and power-up defaults? on page 25 ) to have the data automatically load into the ram at power up, and when en is taken high. table 13-1. ram (0x00 through 0x1f), defaults undetermined. register address register data d7 d6 d5 d4 d3 d2 d1 d0 e2addr 0x60 ? e2addr[6:0] defaults 00000000 eeprom minimum address 0x00 ?0000000 eeprom maximum address 0x51 ?1010001 register address register data d7 d6 d5 d4 d3 d2 d1 d0 e2ctrl 0x61 ? ? ? ? ? rwctrl[2:0] defaults 00000000 eeprom read / write disabled xxxxx 000 read 1 byte from eeprom x x x x x 0 0 1 read 8 bytes from eeprom x x x x x 0 1 0 write 1 byte to eeprom x x x x x 0 1 1 write 8 bytes to eeprom x x x x x 1 0 0 unused x x x x x 1 0 1 x x x x x 1 1 x register name address register data d7 d6 d5 d4 d3 d2 d1 d0 ram 0x00 ? 0x1f ram defaults x x x x x x x x http://www..net/ datasheet pdf - http://www..net/
27 MSL2023/2024 [datasheet] 42063a?led?02/2013 13.2 main string reference volt age register (mref, 0x20) holds the dac value that controls the reference voltage for the main string fet source feedback voltage. the reference voltage equals decimal value of this register times 2mv. the default value for msref is 0x64, which equates to m ref = 200mv. table 13-2. main string reference register (mref, 0x20), defaults highlighted . 13.3 color-adjust string reference voltage register (caref, 0x21) holds the dac value that controls the reference voltage fo r the color-adjust string fet source feedback voltage. the reference voltage equals decimal value of this register time s 2mv. the default value for caref is 0x64, which equates to v caref = 200mv. table 13-3. color-adju st string reference register (caref, 0x21), defaults highlighted . 13.4 fault disable register (fault, 0x22) bits d0 and d1 control the fault response for the color-adjust string. for fault response behavior see ?fault conditions? on page 18 . bit d2 prevents the thermal shutdown fault from pulling fl tb low. write 0x03 to this register to clear faults; write 0x00 to re-enable fault response. register name address register data d7 d6 d5 d4 d3 d2 d1 d0 mref 0x20 mref[7:0] default = 0x64: m ref = 100 * 2mv = 200mv 01100100 m ref = 0 ? 2mv = 0v 00000000 m ref = 255 * 2mv = 510mv 11111111 register name address register data d7 d6 d5 d4 d3 d2 d1 d0 caref 0x21 caref[7:0] default = 0x64: v caref = 100 * 2mv = 200mv 01100100 v caref = 0 ? 2mv = 0mv 00000000 v caref = 255 ? 2mv = 510mv 11111111 http://www..net/ datasheet pdf - http://www..net/
28 MSL2023/2024 [datasheet] 42063a?led?02/2013 table 13-4. fault disable regist er (fault, 0x22), defaults highlighted . 13.5 fault status register (faultstat, 0x23), read only reports the fault status for the color-adjust string. when a faul t is reported in this register, the fault output fltb pulls lo w. toggle en low, then high to clear the faults. faults recur if the fault persists. table 13-5. fault status register (faultstat, 0x23). 13.6 sleep register (sleep, 0x24) puts the device to sleep (the serial interface remains awake). when asleep the gate drive outputs stop switching, and the leds turn off. table 13-6. sleep register (sleep, 0x24), defaults highlighted . register name address register data d7 d6 d5 d4 d3 d2 d1 d0 fault 0x22 ? ? ? ? ? tsdmask ocdis scdis default = 0x00 00000 0 0 0 act on faults xxxxx 0 0 0 disable led short circuit fault xxxxx 0 0 1 disable string open circuit fault xxxxx 0 1 x do not allow thermal shutdown fault to pull fltb low xxxxx 1 x x register name address register data d7 d6 d5 d4 d3 d2 d1 d0 faultstat 0x23 ? ? ? ? ? tsd ocflt ssflt no faults detected xxxxx0 0 0 led short circuit fault detected xxxxx0 0 1 string open circuit fault detected xxxxx0 1 0 the MSL2023/24 is in thermal shutdownxxxxx1 x x register name address register data d7 d6 d5 d4 d3 d2 d1 d0 sleep 0x24 ? ? ? ? ? ? ? sleep default = 0x00 0000000 0 device is awake x x x x x x x 0 device is asleep x x x x x x x 1 http://www..net/ datasheet pdf - http://www..net/
29 MSL2023/2024 [datasheet] 42063a?led?02/2013 13.7 main string duty cycle regist er, high byte (mdutyhigh, 0x34) contains the upper 8-bits of the 12-bit MSL2023 main string duty cycle setting. the remaining 4-bits are in register 0x35. the registers combine to form the main string duty cycl e, a linear relation where 0x000 = 0% to 0xfff = 100%. when changed, the duty cycle updates at the beginning of the next output pwm period. table 13-7. main string duty cycle high register (mdutyhigh, 0x34), defaults highlighted . 13.8 main string duty cycle regi ster, low byte (mdutylow, 0x35) contains the lower 4-bits of the 12-bit MSL2023 main string duty cycle setting. the upper 8-bits are in register 0x34. the registers combine to form the main string duty cycle, a linear relation where 0x000 = 0% to 0xfff = 100%. when changed, the duty cycle updates at the beginning of the next output pwm period. table 13-8. main string duty cycle lo w register (mdutylow, 0x35), defaults highlighted . 13.9 color adjust string du ty cycle register, high byte (cadutyhigh, 0x36) contains the upper 8-bits of the 12-bit MSL2023 color-adjust stri ng duty cycle setting. the remaining 4-bits are in register 0x37. the registers combine to form the color-adjust stri ng duty cycle, a linear relation where 0x000 = 0% to 0xfff = 100%. when changed, the duty cycle updates at the beginning of the next output pwm period. table 13-9. color adjust string duty cycle hi gh register (cadutyhigh, 0x36), defaults highlighted . 13.10 color adjust string duty cycle register, low byte (cadutylow, 0x37) contains the lower 4-bits of the 12-bit MSL2023 color-adjust st ring duty cycle setting. the upper 8-bits are in register 0x36. the registers combine to form the color-adjust stri ng duty cycle, a linear relation where 0x000 = 0% to 0xfff = 100%. when changed, the duty cycle updates at the beginning of the next output pwm period. register name address register name d7 d6 d5 d4 d3 d2 d1 d0 mdutyhigh 0x34 mdutyhigh[11:4] degault = 0xff 1 1 1 1 1 1 1 1 register name address register name d7 d6 d5 d4 d3 d2 d1 d0 mdutylow 0x35 ? ? ? ? mdutylow [3:0] default = 0x0f 000011 1 1 register name address register data d7 d6 d5 d4 d3 d2 d1 d0 cadutyhigh 0x36 cadutyhigh[11:4] default = 0xff 111111 1 1 http://www..net/ datasheet pdf - http://www..net/
30 MSL2023/2024 [datasheet] 42063a?led?02/2013 table 13-10. color adjust string duty cy cle low register (cadut ylow, 0x37), default highlighted . 13.11 efficiency optimizer cont rol register (eoctrl, 0x40) configures three functions associated with the adaptive sourcepower? efficiency optimizer (eo). it is recommended that all eo controls be configured while sleep (bit d0 in the configuration register 0x24) is 1 to avoid perturbations of the string power supply. the MSL2023/24 always perform a po wer supply voltage calibration when power is applied, en is taken high, or sleep is reset to 0. dthresh sets the voltage feedback threshold for d, the main string mosfet drain connection. d threshold = (dthresh*150mv) + 250mv. this is how the device monitors v led to control the magnitude of the eo current. the default value for dthresh is 1v. table 13-11. efficiency optimizer contro l register (fboctrl, 0x40), defaults highlighted . 13.12 registers 0x60 a nd 0x61, eeprom access these registers control access to the eeprom. see ?eeprom and power-up defaults? and ?eeprom address and control/status registers? on page 25 for information. 14. i2c serial interface the MSL2023/24 operate as slaves that send and receive data through an i2c/smbus compatible 2-wire serial interface. the interface is not needed for operation, but is provided to allow control and monitoring of device functions. these functions include changing the string current reference feedback voltages, reading and adjusting the fault response behavior and status, putting the device to sleep without losi ng the register settings, and programming the eeprom. the i2c/smbus compatible interface is suitable for 100khz, 400khz and 1mhz communication. the interface uses data i/o sda and clock input scl to achieve bidirectional communi cation between master and slaves. fault output fltb optionally alerts the host system to faults detected by the MSL2023/24 ( figure 14-1 on page 31 and ?fault conditions? on page 18 ). during over temperature shutdown the serial interface is disabled. the master, typically a microcontroller, initiates all dat a transfers, and generates the clock that synchronizes the transfers. sda operates as both an input and an open-drai n output. scl operates only as an input, and does not perform clock-stretching. pull-up resistors are required on sda, scl and fltb. register name address / default register data d7 d6 d5 d4 d3 d2 d1 d0 cadutylow 0x37 ? ? ? ? cadutylow[3:0] defaults = 0x0f 0 0 0 0 1 1 1 1 register name address register data d7 d6 d5 d4 d3 d2 d1 d0 fboctrl 0x40 reserved[3:0] dthresh[3:0] default = 0xe5 111001 0 1 d threshold = (0 * 150mv) + 250mv = 0.25v 111000 0 0 d threshold = (5 * 150mv) + 250mv = 1v 111001 0 1 d threshold = (15 * 150mv) + 250mv = 2.5v 111011 1 1 http://www..net/ datasheet pdf - http://www..net/
31 MSL2023/2024 [datasheet] 42063a?led?02/2013 figure 14-1. i 2 c interface connections. a transmission consists of a start condition sent by a ma ster, a 7-bit slave address plus one r/w bit, an acknowledge bit, none or many data bytes each separated by an acknowledge bit, and a stop condition ( figure 14-2 , figure 14-4 and figure 14-5 on page 32 ). figure 14-2. i 2 c serial interface timing details. 14.1 i 2 c bus timeout the bus timeout feature allows the MSL2023/24 to reset the serial bus interface if a communication ceases before a stop condition is sent. if scl or sda is low for more than 25ms (typical), then the MSL2023/24 terminates the transaction, releases sda and waits for another start condition. 14.2 i 2 c bit transfer one data bit is transferred during each clock pulse. sda must remain stable while scl is high. figure 14-3. i 2 c bit transfer. master (c) sda int scl sda fltb scl v i2c 2 x 2.2k typical 100k MSL2023 msl2024 start condition repeated start condition star t condition stop condition t hd : st a t r t f t high t low t su : dat t hd : dat t su : st a t hd : st a t su : sto t buf sd a scl sd a scl sda level stable sda data valid sda allowed to change level http://www..net/ datasheet pdf - http://www..net/
32 MSL2023/2024 [datasheet] 42063a?led?02/2013 14.3 i 2 c start and stop conditions both scl and sda remain high when the interface is free. the master signals a transmission with a start condition (s) by transitioning sda from high to low while scl is high. w hen the master has finished communicating with the slave, it issues a stop condition (p) by trans itioning sda from low to high while scl is high. the bus is then free. figure 14-4. i 2 c start and stop conditions. 14.4 i 2 c acknowledge bit the acknowledge bit is a clocked 9th bit which the recipient uses to handshake receipt of each byte of data. the master generates the 9th clock pulse, and the recipient holds sda low during the high period of the clock pulse. when the master is transmitting to the MSL2023/24, the MSL2023/24 pulls sda low because the MSL2023/24 is the recipient. when the MSL2023/24 is transmitting to the master, the master pulls sda low because the master is the recipient. figure 14-5. i 2 c acknowledge. 14.5 i 2 c slave address the MSL2023/24 has a 7-bit long slave address, 0b0100000, followed by an eighth bit, the r/w bit. the r/w bit is low for a write to the MSL2023/24, high for a read from the MSL2023/24. all MSL2023/24 devices have the same slave address; when using multiple devices and communicating with them through their serial interfaces, make external provision to route the serial interface to the appropriate device. note that development systems that use i 2 c often left-shift the address one position before they insert the r/w bit, and so expect a default address of 0x20 (not 0x40). sda scl start condition stop condition s p sda transmitter scl start condition acknowledge by receiver s a sda receiver 12 891 http://www..net/ datasheet pdf - http://www..net/
33 MSL2023/2024 [datasheet] 42063a?led?02/2013 figure 14-6. i 2 c slave address. 14.6 i 2 c message format for writ ing to the MSL2023/24 a write to the MSL2023/24 contains the MSL2023/24?s slave address, the r/w bit cleared to 0, and at least 1 byte of information ( figure 14-7 on page 33 ). the first byte of information is the regi ster address byte. the register address byte is stored as a register pointer, and determines which register the following byte is written into. if a stop condition is detected after the register address byte is received, then the MSL2023/24 takes no further action beyond setting the register pointer. figure 14-7. i 2 c writing a register pointer. when no stop condition is detected, the byte transmitted afte r the register address byte is a data byte, and is placed into the register pointed to by the register address byte ( figure 14-8 ). to simplify writing to multiple consecutive registers, the register pointer auto-increments dur ing each following acknowledge period. further data bytes transmitted before a stop condition fill subsequent registers. figure 14-8. i 2 c writing two data bytes. 14.7 i 2 c message format for reading from the MSL2023/24 the first technique begins the same way as a write, by setting the register address pointer as shown in figure 14-7 , including the stop condition (note that even though the final objective is to read data, the r/w bit is first sent as a write because the address pointer byte is being written into the device). follow the figure 14-7 transaction by what shown in figure 14-9 , with a new start condition and the slave address, this time with the r/w bit set to 1 to indicate a read. then, after the slave initiated acknowledge bit, clock out as many bytes as desired, separated by master initiated sda scl 1 2 3 4 5 6 7 8 9 a7 = 0 a a6 = 1 a5 = 0 a4 = 0 a3 =0 a2 = 0 a1 = 0 r / w msb sda 0 1 0 0000 0 a d7 d0 a acknowledge from msl202x start stop slave address, write access set register pointer to x ...... the register pointer now points to x; a subsequent read access reads from register address x acknowledge from msl202x sda 0 1 0 0000 0 a d7 d0 aa d0 a acknowledge from msl202x start stop slave address, write access set register pointer to x data writes to register x d7 ...... the register pointer now points to x + 2; a subsequent read access begins reading from register address x + 2 acknowledge from msl202x acknowledge from msl202x ...... d7 d0 ...... data writes to register x + 1 acknowledge from msl202x http://www..net/ datasheet pdf - http://www..net/
34 MSL2023/2024 [datasheet] 42063a?led?02/2013 acknowledges. the pointer auto-increments during each master initiated acknowledge period. end the transmission with a not-acknowledge followed by a stop condition. figure 14-9. i 2 c reading register data with preset register pointer. the second read technique is illustrated in figure 14-10 . write to the MSL2023/24 to set the register pointer, send a repeated start condition after the second acknowledge bit, then send the slave address again with the r/w bit set to 1 to indicate a read. then clock out the data bytes separated by master initiated acknowledge bits. the register pointer auto-increments during each master initiated acknow ledge period. end the transmission with a not-acknowledge followed by a stop condition. this technique is recommended for buses with multiple masters, because the read sequence is performed in one uninterruptible transaction. figure 14-10. i 2 c reading register data using a repeated start 14.8 i 2 c message format for broadcast writing to multiple devices with a broadcast write to MSL2023/24, a master broadcasts the same register data to all MSL2023/24s on the bus. first send the broadcast write slave address of 0x00, followed by the MSL2023/24 broadcast device id of 0x42. these two bytes are followed by the register address in the MSL2023/24s that the following data are to be written into, and finally the data byte(s) to be written into all devices. a broadcast write example is shown in figure 14-11 . here, the same register address in every MSL2023/24 is written to with identical data. if further data bytes are transmitted before the stop condition, they are stored in subsequent internal registers of each MSL2023/24. sda 0 1 0 0000 1 a d7 d0 a d0 a acknowledge from msl202x start stop slave address, read access read register address x read register address x + 1 d7 ...... the register pointer now points to x + 2; a subsequent read access reads from register address x + 2 not acknowledge from master ...... acknowledge from master sda 0 1 0 0000 0 a repeated start d0 a 1 1 0000 1 a d0 a acknowledge from msl202x 0 start stop slave address write access slave address read access read registers d7 acknowledge from msl202x acknowledge from msl202x not acknowledge from master ...... d7 ...... set register pointer http://www..net/ datasheet pdf - http://www..net/
35 MSL2023/2024 [datasheet] 42063a?led?02/2013 figure 14-11. i 2 c broadcast writing a data byte. there is no broadcast read. however, a broadcast write may be used to set up the internal register pointers of all the MSL2023/24s in a system to speed up the subsequent individual reading of, for example, all the status registers. figure 14-12 illustrates a broadcast write that sets all the register pointers, and issues a stop. figure 14-12. i 2 c broadcast writing a register pointer. sda 00 000000 a 00 a d0 a acknowledge from msl202x start stop broadcast write slave address msl202x broadcast id sets all register pointers to x data writes to all register xs d7 100001 all register pointers now point to x + 1; the first subsequent read access of each msl202x reads from register address x + 1 acknowledge from msl202x ...... d0 a d7 ...... acknowledge from msl202x acknowledge from msl202x sda 00 000000 a 00 a d0 a acknowledge from msl202x start stop broadcast write slave address msl202x broadcast id sets all register pointers to x d7 100001 all register pointers now point to x; the first subsequent read access of each msl202x begins reading from register address x ...... acknowledge from msl202x acknowledge from msl202x http://www..net/ datasheet pdf - http://www..net/
36 MSL2023/2024 [datasheet] 42063a?led?02/2013 15. packaging information no representation or warranties are made concerning third-party patents with regard to the use of atmel ? products. the mixing of red leds with phosphor-converted leds may be protect ed by certain third-party patents, such as u.s. patent no. 7,213,940 and related patents of cree, inc. http://www..net/ datasheet pdf - http://www..net/
37 MSL2023/2024 [datasheet] 42063a?led?02/2013 16. datasheet revision history 16.1 42063a ? 02/2013 1. initial revision. http://www..net/ datasheet pdf - http://www..net/
i MSL2023/2024 [datasheet] 42063a?led?02/2013 table of contents features 1 typical applications 1 1. introduction 2 2. ordering information 2 3. application circuit 2 4. absolute maximum ratings 3 5. electrical characteristics 4 6. block diagram 12 7. pinout and pin description 14 7.1 pinout ? MSL2023 and msl2024 14 7.2 pin descriptions 14 8. typical application circuit 16 9. detailed description 18 10. fault conditions 18 11. applications information 19 11.1 turn-on sequence 19 11.2 setting the main string current with rs 19 11.3 setting ac/dc output voltage 19 11.4 selecting the main string mosfet 20 11.5 selecting the drain resistor ? rd 20 11.6 selecting the color-adjust string floating buck components 21 11.7 pwm and led brightness 24 12. control registers 24 12.1 eeprom and power-up defaults 25 12.2 eeprom address and cont rol/status registers 25 13. detailed register descriptions 26 13.1 ram (0x00 through 0x1f) 26 13.2 main string reference volt age register (mref, 0x20) 27 13.3 color-adjust string reference voltage register (caref, 0x21) 27 13.4 fault disable register (fault, 0x22) 27 13.5 fault status register (faultstat, 0x23), read only 28 13.6 sleep register (sleep, 0x24) 28 13.7 main string duty cycle register, high byte (mdutyhigh, 0x34) 29 13.8 main string duty cycle register, low byte (mdutylow, 0x35) 29 13.9 color adjust string duty cycle re gister, high byte (cadutyhigh, 0x36) 29 13.10 color adjust string duty cycle register, low byte (cadutylow, 0x37) 29 13.11 efficiency optimizer contro l register (eoctrl, 0x40) 30 13.12 registers 0x60 and 0x61, eeprom access 30 http://www..net/ datasheet pdf - http://www..net/
ii MSL2023/2024 [datasheet] 42063a?led?02/2013 14. i2c serial interface 30 14.1 i2c bus timeout 31 14.2 i2c bit transfer 31 14.3 i2c start and stop conditions 32 14.4 i2c acknowledge bit 32 14.5 i2c slave address 32 14.6 i2c message format for writing to the MSL2023/24 33 14.7 i2c message format for reading from the MSL2023/24 33 14.8 i2c message format for broadcast writing to multiple devices 34 15. packaging information 36 16. datasheet revision history 37 16.1 42063a ? 01/2013 37 table of contents i http://www..net/ datasheet pdf - http://www..net/
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